云南开放大学数字电路及逻辑设计第3次离线作业

.1.

在下面横线上填上合适的语句，完成数据选择器的设计。

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX8 IS

PORT( D:    IN STD_LOGIC_VECTOR(7 OWNTO 0);

SEL:  IN  STD_LOGIC_VECTOR(    1   DOWNTO 0);

Y:    OUT STD_LOGIC_VECTOR);

END;

ARCHITECTURE ONE OF MUX8  IS

BEGIN

WITH       2     SELECT

Y <=  D(0)  WHEN  “000”,

D(1)  WHEN  “001”,

D(2)  WHEN  “010”,

D(3)  WHEN   3   ;

D(4)  WHEN  “100”,

D(5)  WHEN  “101”,

D(6)  WHEN  “110”,

D(7)  WHEN  “111”;

（OTHERS=>‘Z’）WHEN THERS

END;

 

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY MUX4TO1 IS

PORT( A,B,C,D:    IN STD_LOGIC_VECTOR(3 OWNTO 0);

S:  IN  STD_LOGIC_VECTOR(    ①   DOWNTO 0);

Z:    OUT STD_LOGIC_VECTOR(3 DOWNTO 0));

END MUX4TO1;

ARCHITECTURE ARCHMUX  OF MUX4TO1  IS

BEGIN

WITH       ②     SELECT

Z <=  A  WHEN  “00”,

1. B)  WHEN  “01”,

C  WHEN  “10”,

D  WHEN   ③  ;

END ARCHMUX;